The present invention relates to a GaAs planar p-n junction diode and the manufacturing method therefor, and more particularly, to an element isolation technique of a variable capacitor (varicap) diode by means of implanting ions of impurity atoms which renders an element isolation region of the varicap diode to be semi-insulative.
A varicap diode uses a depletion layer capacitance obtained by reversely biasing the p-n junction thereof. The depletion layer capacitance depends on the value of the reverse p-n junction bias. Quality factor Q of such a varicap can be expressed as: EQU Q=1/(2.pi.f Cj rs) (1)
where f denotes a frequency; Cj, a junction capacitance; and rs, an effective series resistance of the junction.
Equation (1) teaches that a large quality factor Q requires a small series resistance rs. Since a prominent reduction in series resistance rs can be achieved by a GaAs substrate, but it cannot be achieved by a Si substrate, a GaAs varicap diode having an excellent mass productivity and a specific manufacturing method therefor have been demanded.
There are two types of GaAs varicap diodes. One is a mesa type and the other is a planar type using a selective ion implantation.
FIG. 4 shows a conventional structure of a planar diode wherein substrate 1 is formed of high-concentration N.sup.+ type GaAs substrate 1a on which low-concentration N.sup.- layer 1b is epitaxially grown. First impurity layer 2 of a high-concentration N.sup.+ type formed in epitaxial layer 1b has a prescribed area for obtaining a desired junction capacitance. Second impurity layer 3 of a high-concentration P.sup.+ type is stacked onto N.sup.+ layer 2, such that P.sup.+ layer 3 has a depth thinner than that of N.sup.+ layer 2 and has an area larger than that of N.sup.+ layer 2. Electrode 4 contacts in ohmic with P.sup.+ layer 3. Other electrode 5 is connected to the back plate of substrate 1a.
A conventional planar varicap diode as shown in FIG. 4 can be made by manufacturing steps illustrated in FIG. 5. First, as shown in FIG. 5(a), substrate 1 is prepared so that epitaxial low-concentration GaAs N.sup.- layer 1b is formed on high-concentration GaAs N.sup.+ layer 1a. Next, as shown in FIG. 5(b), ion implantation mask 2a is formed on substrate 1. Using this mask, a selective ion implantation of Si and annealing thereof are performed so that high-concentration N.sup.+ type first impurity layer 2, having an area for the desired junction capacitance, is formed. In this case, SiO.sub.2, PSG, or a resist formed on SiO.sub.2 or PSG, is used for the material of mask 2a. Then, as shown in FIG. 5(c), ion implantation mask 3a, having an opening slightly larger than the area of mask 2a, is again formed on substrate 1, and mask 3a is overlaid on layer 2 so that high-concentration P.sup.+ type second impurity layer 3, having a smaller depth than N.sup.+ layer 2, is formed by a selective ion implantation of Zn and annealing thereof. Finally, as shown in FIG. 5(d), ohmic electrode 4 connected to P.sup.+ layer 3 is formed by a conventional lift-off method or etching method, and back plate electrode 5, ohmic-contacted to substrate 1a, is formed by a conventional evaporation method and alloy method.
In a planar type varicap manufactured by the above method, the operation area of the varicap is formed by a selective ion implantation. The capacitance vs. reverse-bias voltage characteristic (C-V characteristc) of this varicap has a problem of so-called "C drift". The C drift means that the capacitance of the varicap is unsuitably varied even if the reverse-bias voltage thereof is fixed at a constant value.
For a varicap, the rate of change of its capacitance should exactly and stably depends on that of its reverse-bias voltage. Thus, said C drift is a large problem for a mass-produced planar type varicap diode. This problem can be generally applied to a p-n junction diode structure because a p-n junction has a voltage-dependent capacitance.